Embodiments of the present invention relate to an input buffer circuit, and more specifically, to an input buffer circuit for controlling skew and regulating discrete voltage levels.
Generally, an input buffer transforms a signal of a transistor-transistor logic level into a signal of a complementary metal oxide semiconductor (CMOS) level.
A semiconductor memory device has been applied to a variety of systems. Internal circuits of a semiconductor integrated circuit (IC) are composed of CMOS circuits. Thus, if a level of an external input signal is changed to another level, the external input signal level must be changed to a voltage level usable for a CMOS circuit. Therefore, the semiconductor memory device includes an input buffer in each of an address input end, a data input end, a clock signal input end, and a driving signal input end.
FIG. 1 is a circuit diagram illustrating a conventional input buffer circuit.
Referring to FIG. 1, the input buffer circuit according to the related art includes a comparator 10 and an activation unit 20.
In this case, the comparator 10 compares a reference voltage (VREF) level with an input signal (IN) level, and outputs an output signal OUT according to the result of the comparison. In response to a difference in the input signal (IN) level and the reference voltage (VREF) level, a voltage level of the output signal OUT of the comparator 10 is changed.
The comparator 10 is a current-mirror-type unit amplifier, and includes a plurality of PMOS transistors P1 to P6 and a plurality of NMOS transistors N1 and N2.
Each of the PMOS transistors P1 and P2 is used as a precharge transistor controlled by an enable signal EN. The NMOS transistor N1 receives a reference voltage VREF through a gate terminal. The reference voltage VREF has a voltage level that is half of a power-supply voltage VDDQ. The NMOS transistor N2 receives an input signal IN through a gate terminal.
In addition, the activation unit 20 includes an NMOS transistor N3, which is coupled between the comparator 10 and a ground voltage terminal VSSQ so as to receive the enable signal EN through a gate terminal.
Operations of the aforementioned conventional input buffer circuit are as follows.
First, if the enable signal EN is low in level (or in a low state), the NMOS transistor N3 is turned off, and the PMOS transistors P1 and P2 are turned on, so that the output signal OUT is fixed to a high level irrespective of the input signal (IN) level.
The aforementioned enable signal EN is used to control the input buffer. If the enable signal EN is a low state, the input buffer is not operated and outputs a high level signal. If the enable signal EN is high in level, the input buffer is operated.
Accordingly, if the enable signal EN is high in level, the NMOS transistor N3 is turned on, and the PMOS transistors P1 and P2 are turned off. In this case, if the input signal IN is equal to or higher than the reference voltage VREF, the output signal OUT becomes a low state. Otherwise, if the input signal IN is lower than the reference voltage VREF, the output signal OUT becomes high in level.
As a result, the conventional input buffer changes the input signal (IN) level to a power-supply voltage (VDDQ) level.
However, the aforementioned conventional input buffer circuit is unable to properly cope with variation in characteristics of the input buffer in response to a variation in skew characteristics of transistors.